1. Field of the Invention
The present invention relates to a ferroelectric random access memory (FeRAM), and more particularly to an FeRAM which can compensate for property variations according to positions of cell arrays, by setting different load conditions or changing a size of capacitors according to the positions of each cell array in a multi-bit line structure cell array block.
2. Description of the Background Art
In general, an FeRAM has a data processing speed equivalent to a dynamic random access memory (DRAM), and preserves data even when power is off.
The FeRAM is a memory having a similar structure to the DRAM. The FeRAM employs a ferroelectric substance to form a capacitor, and thus uses high remanent polarization which is a property of the ferroelectric substance. Even if electric fields are removed, data are not deleted in the FeRAM due to the remanent polarization.
The technical descriptions of the FeRAM have been disclosed in Korea Patent application No. 1998-14400 by the same inventors as the present invention. Therefore, detailed explanations of the basic structures and operation principles of the FeRAM are omitted.
In the FeRAM, when a number of cell array blocks increases, the cell array blocks have slightly different operation properties from each other due to physical limits. That is, write or read timing conditions are different in each cell depending on circuit delay time or other conditions.
As a result, as shown in FIG. 1, cell data sensing voltages are regularly shifted for target levels according to positions of cell arrays due to the design factors. Such a non-uniform phenomenon leads to deterioration of properties of cell data.